Arithmetic Logic Unit (ALU) with FPGA

Objectives:
In this laboratory you will use the design tools for Xilinx Field Programmable Gate Array (FPGA) circuit implementations to design and test a small adder/subtractor (ALU) unit. The circuit will allow  two three bit input values to be added or subtracted. Your input data will be set using switches on the FPGA demo board. The output will be a four bit value which will be displayed on the seven segment display. You will view your input values on LEDs. In your prelab you will create your circuit with the appropriate library for the FPGA. You will also design a systematic test plan to test your circuit since there will be 128 different input combinations (2⁹) and you will not want to test all of them individually. In the lab you will download your design to a demonstration board and test it using your test plan.

Adder/Subtractor Circuit Specification: The circuit that you will design will use a four-bit adder from the Xilinx library to do several possible operations on two three bit data inputs. A three-bit field will specify which of the operations will be performed. This can be interpreted as an operation code. Two three-bit data inputs will provide the values to be used in the operation. These are often called operands. The operations are specified in the table below. The output will be a four-bit value.
 

PreLab:
1.Be sure you understand 2's complement representation of signed numbers. The four bit adder can be used for all operations since (-B) represented in 2's complement form can be added in the same way as (+B). You would only have to choose between B and B' at the adder inputs.

2. Fill in the connection table below for your adder for each of the operations listed. (Note: The transfer can be implemented with two different combinations of B input and Carry input) This is similar to the ALU described in Table 7-7 on page 361 of the text, but the selects are used in a different way. The first several operations have been done for you.

4. You can use MUXes and other logic gates along with the 4 bit adder to build this arithmetic unit. Write the logic equation for each of the adder inputs. Try to make a small efficient circuit.

5. Note that the adder expects four bits for each input and we are providing only three bit inputs. Make sure you connect the most significant bits of the inputs, a3 and b3, to the appropriate level according to the operation to be performed. For example: a3="0" and b3="0" when the operation is A+B and a3="0" and b3 ="1" when the operation is A-B.

6. Draw the schematic for your design using the Xilinx libraries. Be sure that all inputs to your components are controlled and are not left floating.

7. Connect the inputs to your circuit to the 8 switches on the board. Each input must come from an IPAD and have an IBUF connected to the IPAD. Refer to the table for pad/pin numbers for switches of the demo board.

• a0 is connected to SW1, a1 is connected to SW2, a2 is connected to SW3,
• b0 is connected to SW4, b1 is connected to SW5, b2 is connected to SW6,
• s0 is connected to SW7 and s1 is connected to SW8.  Since there are only 8 switches and we need nine inputs, we will use pushbutton 1 for s2. The button normally has a low output unless it is pressed. We will simply tie the point high in lab instead of holding the button down.

8. In order to observe the inputs and outputs of your circuit you will connect them to LEDs and to seven segment displays. Remember that a signal which will be connected to an LED or a seven segment display must be connected to the OPAD through an OBUF. Refer to the table for pad/pin numbers for LEDs and seven-segment display of the demo board.

Information on how the seven segment display works is given in the digilent board specifications under seven segment display.

• Connect the input numbers A and B to LEDs. A0 is connected to LD1. A1 is connected to LD2. A2 is connected to LD3.
• b0 is connected to LD4. b1 is connected to LD5. b2 is connected to LD6.
• Connect the carry output of your adder to LD7 and overflow (OF) output of your adder to LD8.

The sum output will be displayed using one of the seven segment displays and we will choose display 1. The displays all use the same cathode signals to turn individual segments on and off. Each has its own anode signal so that the whole display can be turned off. The anode for  display 1 has to be on and so connect the pad A1 to logic 1. NOTE: this is a designation of the digilent board for a particular signal and it is NOT the same as our data input a1 which is connected to an input switch. The other anodes A2, A3, A4 need to be at logic 0, so that they will be turned off.

Create a seven segment display decoder to display the value of the sum using seven ROM16x1 components (each ROM is used for one  segment of the seven segment display). Make a truth table for each segment for the displayed images  0 to F as shown in the figure at the end of the prelab. Use these truth tables to determine the INIT value for each ROM.  From your TT, determine the Hex Code for each of segment. For example, for segment G, the binary value from the TT table from bottom (F image) to top (0 image) is is 1110 1111 0111 1100 or EF7C in hexadecimal. You need to "click" on the ROM to change the parameter value INIT, which is initially set to 0000. Connect the output of the each ROM to the cathode of the segments of the display. For the display segment to turn on the cathode, it needs to be 0. Therefore you need to invert the ROM output before it goes to the OBUF and OPAD for the cathode of that segment. For example the output for the ROM for CG (with INIT value EF7C) will be inverted and go to Output Pad# 45 through an OBUF.

9. Design a test plan to debug your circuit so that you detect a significant number of circuit faults. An example of the beginning of a plan is given here:

• TEST: Set all data input switches to zero. Observe the output on the LEDs and seven segment display.Set the operation to A+B (s2s1s0 = 100)
• EXPECTED RESULT: All LEDs should be off. The seven segment displays should show a '0'.
• PURPOSE OF TEST: This is a very basic test of the input connections since it should be adding A+B with both inputs 0. Since the LEDs and the seven segment displays are our only indicators of how the circuit is functioning, we should test them first to see if they are working correctly.
• POSSIBLE PROBLEMS: If the seven segment displays are not correct check both the input connections and the INIT values for the ROMs.

• TEST: Set the switch input for a0 to a 1 while all other switch inputs are 0. Repeat for a1 and a2. Repeat for b0, b1, and b2.
• EXPECTED RESULT: ???
• PURPOSE OF TEST: This will test that each of the input bits is connected in the correct order. For example if A=1, B=0, and the output is 4, then either A or the output is connected in reverse order.

10. Submit the circuit schematic and any necessary work such as truth tables as your prelab. Also submit your plan for steps 3 and 4 of the test procedure discussed above.

Note that in this is similar to the BCD to seven-segment decoder described on page 109 of the text. However, in this lab we will want to be able to identify all 16 possible output bit patterns so 16 different patterns will be needed and there will not be any "don't care" input conditions.

Lab:
1. Download your circuit design to the FPGA on a demo board and check that the operation is correct using your test plan.

2. When your test plan has been successful, demonstrate the operation to your laboratory assistant, who will test several input combinations. Test the circuit for these combinations and write the values observed for the 4 output bits of the Adder and the carry and overflow. Be prepared to explain to the lab assistant why the carry and overflow are 1 for the examples you have recorded.
 

Lab report:

1.  For each of the operations, what is the full range of the outputs if the inputs are interpreted as unsigned three-bit integers? (i.e., what is the minimum and maximum values can your outputs display?)

2. Estimate how many CLBs are needed for each component of your circuit. Assume that each 4-bit adder is created from four bit slice adders which each accept three inputs (Ak, Bk, Cin) and create two outputs (Sk, Cout). Remember that each CLB can create 2 outputs that are functions of up to four inputs. Compare your estimate to the actual number of CLBs used in your circuit.

3. The circuit created in this lab used three bit unsigned inputs and created a four-bit output and a carry. Consider the carry as a fifth bit and interpret the results you recorded in your table as follows.

• Interpret the result as a five bit 2's complement number. Which results are incorrect because of an overflow?
• Interpret the result as a four bit unsigned number. Which results are incorrect because of an overflow?
• Interpret the result as a four bit 2's complement number. Which results are incorrect because of an overflow?
• Interpret the result as a three bit unsigned number. Which results are incorrect because of an overflow?
• Interpret the result as a three bit 2's complement number. Which results are incorrect because of an overflow?

4. How would you modify your circuit to handle four bit inputs in 2's complement form? (i.e., inputs representing values from -8 to +7). Indicate what circuitry you would add to detect overflow conditions.

5. If you connected your four adder outputs directly to the cathodes CA, CB, CC, and CD instead of using your seven segment display decoder, what would you expect to see for the 16 outputs?

6. Consider the following conditions for testing your circuit:

• What input sequence would you use to determine if a2 and a1 had been switched in the wiring from your switches to the adder? At which step in your test procedure would you have found this?
• If you suspected that b2 was always low regardless of what the switch setting how would you verify that?
• What would your seven segment display look like if you did not invert the outputs specified in your truth table?