**STATIC HAZARDS **

A static hazard occurs when a single input variable change should cause no change in the output of a combinational logic circuit, but a short glitch of the incorrect logic level occurs. The problem occurs because real physical implementations of logic functions have finite propagation times which are variable, and if two inputs to a gate should theoretically change simultaneously, one will actually change before the other. If more than one input variable changes "simultaneously" there is no way to guarantee that such glitches will not occur.

For example, for an OR gate with inputs R and S, if R=1 and S=0, the output will be 1. If both inputs change "at the same time", the output should remain 1. However, if R changes first, there will be a short interval before S changes when the output will go to 0. This is called a static 1 hazard if this simultaneous change in R and S is caused by a single input variable change.

Similarly, for an AND gate with inputs U and V, if U=1 and V=0, the output will be 0. If both inputs change "at the same time", the output should remain 0. However, if V changes first, there will be a short interval before U changes when the output will go to 1. This is called a static 0 hazard if this simultaneous change in U and V is caused by a single input variable change.

**STATIC 1 HAZARDS **

A static 1 hazard may occur in a two level sum of products (SOP) implementation. Consider an AND-OR SOP implementation with the following characteristics:

- For the current input conditions only one AND gate has a logic '1' output. This causes the output of the OR to be '1'.
- A single input variable changes which "simultaneously" causes the first AND gate output to a logic '0' and causes another AND gate output to go to a logic '1'.

If the first AND gate changes before the second, the OR will have two '0' inputs for a short time and an output glitch will occur. For example, consider the function f(A,B,C) = A'B+AC implemented in this minimized SOP form. In this case R=A'B and S=AC so f(A,B,C)=R+S. When the inputs change from ABC=111 to ABC=011, a glitch as described above can occur. If it does not occur on this transition, it will occur on the reverse transition from ABC=011 to ABC=111.

**Detection of Static 1 Hazards: **

A static one hazard can be detected by observing the products used for the function on a K-map. If any two logically adjacent cells with a '1' output are not covered by a common product or implicant, a static hazard can occur when a single input change moves from one cell to the other. In the example above, the cells for minterms 3 and 7 both contain '1', but minterm 3 is covered by product A'B and minterm 7 is covered by product AC. There is no product which covers them both.

BC
\ A |
00 | 01 | 11 | 10 | ||||

0 | 0 | 0 | 1 | 1 | R=A'B | |||

1 | 0 | 1 | 1 | 0 | S=AC | |||

f(A,B,C)=R+S=A'B+AC |

A static hazard can also be detected algebraically. If only the distributive law is used to convert the SOP form to a POS form and the resulting POS form contain the sum of a variable and its complement, then this is an indication of a static 1 hazard. Although algebraically the sum of a variable and its complement is always '1', due to different delay paths in the circuit it might appear that for a short interval both the variable and its complement are 0. In the example above

f(A,B,C)=A'B+AC = (A'B+A)(A'B+C)=(A'+A)(B+A)(A'+C)(B+C)

has a sum (A'+A). Due to variable delays in different branches of the circuit, this sum may be effectively zero for very short time intervals. If all other sums are '1', then the output should stay '1', but since they are all ANDed with (A'+A), its momentary zero would cause an output glitch which would be a static 1 hazard.

**Prevention of Static 1 Hazards:**

A static 1 hazard an be prevented by adding a product terms so that all pairs of logically adjacent cells with a '1' output have at least one common product covering them. This can be accomplished by using all prime implicants in the SOP form rather than using a minimized SOP form. In the example above the hazard free form will be f(A,B,C) = A'B+AC + BC where the product BC has been added to cover both minterms 3 and 7. Note also that the hazard condition occurred with transitions between ABC = 111 and 011, and this product output does not change during this transition.

BC
\ A |
00 | 01 | 11 | 10 | ||||

0 | 0 | 0 | 1 | 1 | R=A'B | |||

1 | 0 | 1 | 1 | 0 | S=AC | |||

f(A,B,C)=R+S=A'B+AC+BC |

**Additional Notes about Static 1 Hazards:**

A SOP form with AND-OR implementation can never have a static '0' hazard. If the output is a zero both before and after a single variable change, then all products must be '0' both before and after the single variable change, so no input to the OR gate will change and ho hazard can occur. Everything stated above for the two level AND-OR implementation is also true for the two level NAND-NAND implementation. For a large number of variables it is possible to have two logically adjacent minterms with '1' output that are each covered by multiple products but not both covered by a common product. This will still cause a hazard condition. The hazard will only be avoided by having a common product covering the pair, not just by having multiple products cover each minterm.

**STATIC 0 HAZARDS **

A static 0 hazard may occur in a two level product of sums (POS)implementation. Consider an OR-AND POS implementation with the following characteristics:

- For the current input conditions only one OR gate has a logic '0' output. This causes the output of the AND to be '0'.
- A single input variable changes which "simultaneously" causes the first OR gate output to a logic '1' and causes another OR gate output to go to a logic '0'.

If the first OR gate changes before the second, the AND will have two '1' inputs for a short time and an output glitch will occur. For example, consider the function f(A,B,C) = (A+B)(A'+C) implemented in this minimized POS form. In this case U=(A+B) and V=(A'+C) so f(A,B,C)=(U)(V). When the inputs change from ABC=100 to ABC=000, a glitch as described above can occur. If it does not occur on this transition, it will occur on the reverse transition from ABC=000 to ABC=100.

**Detection of Static 0 Hazards: **

A static zero hazard can be detected by observing the sums used for the function on a k-map. If any two logically adjacent cells with a '0' output are not covered by a common sum, a static hazard can occur when a single input change moves from one cell to the other. In the example above, the cells for maxterms 0 and 4 both contain '0', but maxterm 0 is covered by sum (A+B) and maxterm 4 is covered by sum (A'+C) . There is no sum which covers them both.

BC
\ A |
00 | 01 | 11 | 10 | ||||

0 | 0 | 0 | 1 | 1 | U=A+B | |||

1 | 0 | 1 | 1 | 0 | V=A'+C | |||

f(A,B,C)=UV=(A+B)(A'+C) |

A static hazard can also be detected algebraically. If only the distributive law is used to convert the POS form to a SOP form and the resulting SOP form contains the product of a variable and its complement, then this is an indication of a static 0 hazard. Although algebraically the product of a variable and its complement is always '0', due to different delay paths in the circuit it might appear that for a short interval both the variable and its complement are 1. In the example above

f(A,B,C)=(A+B)(A'+C)=A(A'+C)+B(A'+C)=AA' + AC + BA' +BC

has a product (AA'). Due to variable delays in different branches of the circuit, this product may be effectively one for very short time intervals. If all other product are '0', then the output should stay '0', but since they are all ORed with (AA'), its momentary one would cause an output glitch which would be a static 0hazard.

**Prevention of Static 0 Hazards: **

A static 0 hazard an be prevented by adding sum terms so that all pairs of logically adjacent cells with a '0' output have at least one common sum covering them. This can be accomplished by using all prime implicants in the POS form rather than using a minimized POS form. In the example above the hazard free form will be f(A,B,C) = (A+B)(A'+C)(B+C) where the sum (B+C) has been added to cover both maxterms 0 and 4. Note also that the hazard condition occurred with transitions between ABC = 100 and 000, and this product output does not change during this transition.

BC
\ A |
00 | 01 | 11 | 10 | ||||

0 | 0 | 0 | 1 | 1 | U=A+B | |||

1 | 0 | 1 | 1 | 0 | V=A'+C | |||

f(A,B,C)=UV=(A+B)(A'+C)(B+C) |

**Additional Notes about Static 0 Hazards: **

A POS form with OR-AND implementation can never have a static '1' hazard. If the output is a one both before and after a single variable change, then all sums must be '1' both before and after the single variable change, so no input to the AND gate will change and ho hazard can occur. Everything stated above for the two level OR-AND implementation is also true for the two level NOR-NOR implementation. For a large number of variables it is possible to have two logically adjacent maxterms with '0' output that are each covered by multiple sums but not both covered by a common sum. This will still cause a hazard condition. The hazard will only be avoided by having a common sum covering the pair, not just by having multiple sums cover each maxterm.

Supplemental Material for ELEN 021, Logic Design

**(c) Copyright 1997 Sally L, Wood**